The disclosure relates to the technical field of display and in particular relates to a driving apparatus, display apparatus and driving method.
With continuous development of the flat-panel display technology, more and more display apparatus are designed with a dual-gate (Dual Gate) structure in order to, for example, reduce the production cost. With the dual-gate design, as shown in FIG. 1, the number of gate lines doubles, while the number of data lines reduces by half. In each row of pixel units, the odd columns of pixel units are connected to the same gate line and the even rows of pixel units are connected to another adjacent gate line. In particular, as shown in FIG. 2, the data is written in a Z-pattern during the display driving process. Specifically, during a first scan cycle, the gate line GO1 is at a high level, the thin film transistors of the odd columns of pixel units in the first row of pixel units are turned on and the data line receives a data signal to charge the odd columns of pixel units in the first row of pixel units; during a second scan cycle, the gate line GO2 is at a high level, the thin film transistors of the even columns of pixel units in the first row of pixel units are turned on and the data line receives a data signal to charge the even columns of pixel units in the first row of pixel units. Similarly, the gate lines GO3, GO4, . . . , and GO10 are sequentially at a high level and cooperate with the data line to charge the corresponding pixel units.
To avoid damage to the liquid crystal molecules caused by driving the liquid crystal molecules always using the positive voltage or negative voltage, it has been proposed in the prior art to drive the liquid crystal molecules by using the positive and negative voltages alternately. In other words, the polarities of the data signal on the same data line inverted after multiple scan cycles. The source driving circuit 32 needs a period of rising delay time (Rising Time) to output the data signal when the polarity inversion of the data signal occurs. As a result, the data writing time of the pixel units when the polarity inversion of the data signal occurs is shorter than that of the pixel units when the polarity inversion of the data signal does not occur. Accordingly, certain columns of pixel units are charged for relatively longer time while other columns of pixel units are charged for relatively shorter time. As shown in FIG. 2, with the ‘2Line’ polarity inversion mode as an example, the voltage at which the SO1 writes to the R(GO1) has not reached a steady state yet when the gate line GO1 is at a high level; similarly, the voltage at which the SO1 writes the R(G03) has not reached a steady state yet when the gate line GO3 is at a high level, and so on; while the voltage at which the SO1 writes G(G02), G(G04), G(G06) . . . has already reached a steady state. As a result, V-line phenomenon occurs, i.e., the left and right pixel units are of uneven brightness, e.g., one pixel unit is relatively darker while the other is relatively brighter. Therefore, it has become a research focus as to how to achieve even brightness and avoid V-line phenomenon caused by uneven brightness of the pixel units.